The present invention relates to an apparatus and method for optical evaluation suitable for use in in-line property evaluation performed in the process of manufacturing a semiconductor device, to an apparatus and method for manufacturing a semiconductor device utilizing optical evaluation, a method of controlling the apparatus for manufacturing a semiconductor device, and a semiconductor device to be subjected to optical evaluation.
As ever-higher integration has been achieved in recent semiconductor integrated circuits, increasing miniaturization and higher performance have been required of a transistor element to be mounted on a MOS semiconductor device. In particular, the increasing miniaturization of the transistor element has created the demand for a MOS device having high reliability. To implement the MOS devices having high reliability, however, each component of the MOS device should have high reliability.
For example, the reliability of a contact portion, which is dependent on a method of forming a contact window, is an important factor in determining the reliability of such a MOS device. When a damaged layer is produced in a semiconductor substrate by dry etching performed to form the contact window, it is removed by wet etching subsequent to the dry-etching process. To estimate the proper amount of removal, a conventional method of manufacturing a semiconductor device has used a wafer for monitoring, not for products, to measure the electric property thereof and thereby determine the depth of the damaged layer produced during the dry-etching process. The wet-etching process for removing the damaged layer is performed under such conditions as a duration of time and a temperature that have been determined based on the electric property. Thus, the conventional method of manufacturing a semiconductor device has optimized processing conditions during the manufacturing process based on the electric property obtained by using the wafer for monitoring.
In the process of forming the individual components of a semiconductor device, the technology of impurity introduction, e.g., plays an important role in determining the operational properties of the semiconductor device. Ion implantation is a predominant method for impurity introduction, whereby impurity ions from ion source are accelerated with the application of an electric field and thereby allowed to enter a semiconductor substrate or an electrode. During the ion implantation, impurity ions are normally accelerated with energy of several tens of kiloelectron volts before entering the semiconductor substrate or the like. However, the implantation of the impurity ions has caused a crystallographically damaged layer in the surface of the semiconductor substrate or the like. In addition, the impurity has not been activated as carriers, while the concentration of the impurity has not optimumly been distributed. For the activation of the impurity, recovery from the damage, and optimization of profiles, a heat treatment (annealing) has typically been performed after ion implantation. Conventionally, the annealing process time, temperature, and the like have been determined through the optimization of design (device simulation) and conditions. In principle, conditions for annealing have been determined empirically. In particular, an annealing process for recovery from the surface damaged layer of the semiconductor substrate has been performed empirically.
As for a gate insulating film used in a MOS device, the thickness thereof has increasingly been reduced at a high pace, so that an extremely thin insulating film with a thickness of 4 nm or less will probably be used in the 21st century. In a MOS device having such an extremely thin insulating film, the properties of the insulating film may determine the properties of the entire CMOS device and hence the electric property of the whole semiconductor integrated circuit. Therefore, the properties of the insulating film are considered to be particularly important.
The properties of such a gate insulating film have conventionally been controlled by forming a MOS capacitor or MOS transistor and evaluating the electric property thereof. The evaluation of the electric property is performed during or after the manufacturing of a MOS device by retrieving a wafer with the MOS device mounted thereon from a chamber.
With the increasing miniaturization of the MOS device as described above, the conventional evaluation method has presented the following problems in the processes of etching, introducing an impurity, and forming a gate insulating film.
First, the etching process has the following problems. While the two-dimensional size (horizontal size) of the contact window has been reduced increasingly, the depth of the contact window has not been reduced, resulting in an increased aspect ratio (ratio of the depth to the horizontal size). To form such a contact window with a high aspect ratio, a high-vacuum/high-density plasma has been used in, e.g., a dry-etching process. The high-vacuum/high-density plasma process has successfully formed a deep contact window by using highenergy ions in vertical directions. However, the bombardment of the high-energy ions has caused a more seriously damaged layer having a greater depth in the semiconductor crystal of the bottom of the contact window than has been caused by conventional dry etching using a comparatively low-vacuum/low-density plasma. In the case of using light of a wavelength in the microwave range (such as an infrared ray) to evaluate a damaged layer, light itself enters the Si substrate and reaches a point at a depth of more than 1 .mu.m from the surface thereof, so that it is impossible to precisely evaluate damage on a level of several tens of nanometer caused actually by the plasma to the Si substrate. In spite of the future trend toward an increasingly miniaturized LSI, it has become substantially impossible to accurately evaluate a thin damaged layer formed only at the surface as well as an extremely miniaturized region.
Hence, it has become difficult to ensure the removal of the damaged layer with excellent controllability by using only the conventional evaluation method.
Next, the impurity introducing process and the annealing process have the following problems. With the miniaturization of individual elements in a semiconductor device, profile control as well as impurity introduction in a miniaturized region has played an increasingly important role. However, in accordance with the conventional method in which annealing conditions are set empirically, optimum profiles cannot be obtained or trouble occurs oftentimes as a result of terminating the process with a defect remaining in a semiconductor substrate. Moreover, a developing efficiency will be reduced significantly if annealing conditions are optimized by the conventional procedure consisting of processing and analysis repeatedly performed in this order, while a shorter period of time is required to develop a desired semiconductor device. Under such circumstances, process control technology using an in-situ observation technique for the annealing process has been in recent demand. In performing heat treatment by using single-wafer heat treatment apparatus, slight variations are observed in the amount of heat treatment performed with respect to different wafers. The variations may be attributed to the properties of the single-wafer heat treatment apparatus which are intrinsically different or have varied with time, unlike conventional heat treatment apparatus for batch processing. Furthermore, it is also difficult to precisely determine an actual dose for impurity introduction and the effective concentration of the impurity introduced into the substrate after heat treatment.
Th process of forming a gate insulating film has the following problem. In the case of controlling the properties of the gate insulating film by the conventional method of evaluating the electric property, even when any trouble occurs in the process of forming the insulating film, the trouble will be discovered only after the wafer is retrieved from the chamber after the completion of the process and the electric property thereof is evaluated. Until then, the gate insulating film having the trouble will have been manufactured without interruption, resulting in a reduced productivity (efficiency).